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january 2008 rev 1 1/37 UM0470 user manual stm8 swim communication protocol and debug module introduction this manual has been written for developers who need to build programming, testing or debugging tools for the stm8 microcontroller family. it explains the debug architecture of the stm8 core. the stm8 debug system consists of 2 modules. dm - debug module swim - single wire interface module related documentation stm8 flash programming reference manual (pm0047) www.st.com
contents UM0470 2/37 contents 1 debug system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 communication layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 single wire interface module (s wim) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 swim entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3.1 high speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.2 low speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 swim communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 swim commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5.1 srst: system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5.2 rotf: read on the fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5.3 wotf: write on the fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 swim communication reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 cpu register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 swim communication in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10 stm8 swim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10.1 swim control status register (swim_csr) . . . . . . . . . . . . . . . . . . . . . . 15 3.10.2 swim clock control register (clk_swim ccr) . . . . . . . . . . . . . . . . . . . 17 4 debug module (dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.2 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.3 abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.4 watchdog control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.5 interaction with swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 breakpoint decoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UM0470 contents 3/37 4.5 software breakpoint mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.8 data breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9 instruction breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.10 step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11.1 illegal memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11.2 forbidden stack access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11.3 dm break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.12 dm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12.1 dm breakpoint register 1 extended byte (dm_bkr1e) . . . . . . . . . . . . . 28 4.12.2 dm breakpoint register 1 high byte (dm_bkr1h) . . . . . . . . . . . . . . . . . 28 4.12.3 dm breakpoint register 1 low byte (dm_bkr1l) . . . . . . . . . . . . . . . . . . 28 4.12.4 dm breakpoint register 2 extended byte (dm_bkr2e) . . . . . . . . . . . . . 29 4.12.5 dm breakpoint register 2 high byte (dm_bkr2h) . . . . . . . . . . . . . . . . . 29 4.12.6 dm breakpoint register 2 low byte (dm_bkr2l) . . . . . . . . . . . . . . . . . . 29 4.12.7 dm control register 1 (dm_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.12.8 dm control register 2 (dm_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.12.9 dm control/status register 1 (dm_csr1) . . . . . . . . . . . . . . . . . . . . . . . 32 4.12.10 dm control/status register 2 (dm_csr2) . . . . . . . . . . . . . . . . . . . . . . . 33 4.12.11 dm enable function register (dm_enfctr) . . . . . . . . . . . . . . . . . . . . . 34 4.12.12 summary of swim, dm and core register maps . . . . . . . . . . . . . . . . . . 35 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
debug system overview UM0470 4/37 1 debug system overview the stm8 debug system interface allows a debugging or programming tool to be connected to the mcu through a single wire bidirectional communication based on open-drain line. it provides non-intrusive read/write access to ram and peripherals during program execution the block diagram is shown in figure 1 . figure 1. debug system block diagram the debug module uses the two internal clock sources present in the device, the lsi low speed internal clock (usually in the range 30 khz-200 khz, depending on the product) one and the hsi high speed internal clock (usually in the range 10 mhz to 25 mhz, depending on the device). the clocks are auto matically started when necessary. swim entry lsi oscillator hsi oscillator comm layer command decode debug module (dm) stm8 core peripherals swim pin peripheral bus cpu bus swim module ram flash/ ram bus stm8 data eeprom
UM0470 communication layer 5/37 2 communication layer the swim module is a single wire interface based on asynchronous, high sink (8 ma), open-drain, bidirectional communication. while the cpu is running, the swim module allows non-intrusive read/write accesses to be performed on-the-fly to the ram and peripheral registers, for debug purposes. in addition, while the cpu is stalled, the swim module allows read/write accesses to be performed to any other part of the mcu? s memory space (data eeprom and program memory). cpu registers (a, x, y, cc, sp) can also be accessed. these registers are mapped in memory and can be accessed in the same way as other memory addresses. register, peripherals and memory can be accessed only when the swim_dm bit is set. when the system is in halt, wfi or readout protection mode, the no_access flag in the swim_csr register is set. in this case, it is forbidden to perform any accesses because parts of the device may not be clocked and a read access could return garbage or a write access might not succeed. the swim module can perform a mcu device software reset. the swim pin can also be used by the mcu target application as a standard i/o port with some restrictions if you also want to use it for debug. the safest way is to provide a strap option on the application pcb. figure 2. swim pin external connections stm8 application i/o swim interface for tools jumper selection for debug purposes swim pin
single wire interface module (swim) UM0470 6/37 3 single wire interface module (swim) 3.1 operating modes after a power-on reset (powering of the device) the swim module is reset and enters in its off mode. 1. off : in this mode the swim pin must not be used as an i/o by the application. it is waiting for the swim entry sequence or to be switched to i/o mode by the application software. 2. i/o : this state is entered by the software application by setting the iom bit in the core configuration register (mcr). in this state, the user application can use the swim pin as a standard i/o pin, the only drawback is that there is no way to debug the functionality of this pin with the built-in debug capabilities. in case of a reset, the swim goes back to off mode. 3. active : this mode is entered when a specific sequence is detected on the swim pin while in off state. in this state, the swim pin is used by the host tool to control the stm8 with 3 commands. (srst system reset, rotf read on the fly, wotf write on the fly) note: please note that the swim can be set active and communicate while the device is in reset state (nrst pin forced low) figure 3. swim module activation sequence por active i/o off iom bit set y swim entry sequence y rotf wotf rst bit set reset n n y n csr srst
UM0470 single wire interface module (swim) 7/37 3.2 swim entry sequence after a por, and as long as the swim module is in off mode, the swim pin is sampled for entry sequence detection. in order to do this, the internal low speed rc clock is automatically turned on after por and remains forced on as long as the swim is in off mode. if the register which forces the swim module in i/o mode is written before the entry sequence is finalized, the swim module enters i/o mode. once the swim module is active, writing this bit has no influence on communication and the swim interface remains in active mode. if an application uses the swim pin as standard i/o, it puts the swim interface in i/o mode in the initialization sect ion of the software code (typically, this is performed just after the reset). however, even in this case, it is st ill possible to put the sw im interfac e in active mode by forcing the reset pin to 0 and keep it low for the duration of the swim entry sequence. as long as the swim module is in off mode, the swim entry sequence is detected at any moment, during reset or when the application is running. if both the swim pin and the reset pin are multiplexed with i/os, the way to enter swim active state is to power down the mcu device, power up and to maintain the reset until the end of the swim entry sequence. figure 4. swim activation timing diagram swim swim entry sequence communication (1) (2) (3) (4) lsi osc on hsi osc on (5) swim active set swim_csr(5) set pin
single wire interface module (swim) UM0470 8/37 swim activation is shown on figure 4 and each segment on the diagram is described below. 1. to make the swim active, the swim pin must be forced low during a period of several s. 2. after this first pulse at 0, the swim module will detect a specific sequence to guarantee robustness in the swim active state entry. the swim entry sequence is: 4 pulses at 1 khz followed by 4 pulses at 2 khz. the frequency ratio is detected and allows swim entry. the ratio can be easily detected whatever internal rc frequency. the waveform of the entry sequence is shown figure 5 . 3. after the entry sequence, the swim enters in swim active state, and the hsi oscillator is automatically turned on. 4. in most cases, swim entry is done when the reset line is active (low). in order to perform device calibration, the tool must re lease the reset line and calibrate the clock by sending a ?swim communication reset? command after the option bytes loading phase, in order to reach a precision of +/- 4%. the duration of this phase is 64 x hsi clock periods. 5. after this delay, the swim module sends a synchronization frame to the host. synchronization frame description: a synchronization frame of 128 x hsi clock periods with the swim line at 0 is sent out by the mcu device to allow for the measurement of the rc by the debug host. an advanced debug host can re-calibrate its clock to adapt to the frequency of internal rc. 6. before starting a swim communication, the swim line must be released at 1 to guarantee that the swim module is ready for communication (at least 300 ns). figure 5. swim entry sequence 3.3 bit format the bit format is a return-to-zero format, which allows synchronization of every bit. two communication speeds are available. at swim activation, the low speed is selected. the high speed is selected by setting the hs bit in the swim_csr register with the swim protocol. when entering swim mode during the reset phase, it is possible that the option bytes have not yet been loaded from non volatile memory to their respective registers. option byte loading is triggered by any internal or external reset. in order to ensure proper system behavior, the hs bit should not be set until the option byte loading is finished. at the end of the option byte loading, the obl bit in the swim_csr is set by hardware. swim pin swim module active 1 ms 500 s swim entry sequence
UM0470 single wire interface module (swim) 9/37 3.3.1 high speed bit format 1 bit is generated with ten hsi oscillator pulses. the bit format is: - 2 pulses at ?0? followed by 8 pulses at ?1? for ?1? value. - 8 pulses at ?0? followed by 2 pulses at ?1? for ?0? value. when the swim module receives a data packet, it will decode: - ?1? when the number of consecutive samples at ?0? is less or equal to 4. - ?0? when the number of consecutive samples at ?0? is greater or equal to 5. figure 6. high speed bit format 3.3.2 low speed bit format 1 bit is generated with twenty-two hsi oscillator pulses. the bit format is: - 2 pulses at ?0? followed by 20 pulses at ?1? for ?1? value. - 20 pulses at ?0? followed by 2 pulses at ?1? for ?0? value. when the swim module receives a data packet, it will decode: - ?1? when the number of consecutive samples at ?0? is less or equal to 8. - ?0? when the number of consecutive samples at ?0? is greater or equal to 9. figure 7. low speed bit format <=> ?1? <=> ?0? <=> ?1? <=> ?0?
single wire interface module (swim) UM0470 10/37 3.4 swim communication protocol when in active mode, communication can be initiated by host or device. each byte or command is preceded by a 1-bit header in order to arbitrate if both host and device initiate the communication at the same time. the host header is ?0? in order to have the priority over the device in case of arbitration, due to open-drain capability. the ho st can start the transfer only if there is no transfer on-going. figure 8. . command format (host -> target) each command sent by the host is made of: 1 command (rotf, wotf or swrst) made of header: 1 bit at ?0? b2-b0: 3-bit command pb: parity bit: xor between all b(i) ack:acknowledge (1 bit at ?1?). the receiver must send the not-acknowledge value if it has detected a parity error (nack: not acknowledge = 1 bit at ?0?), or it is not yet ready. and optionally several data packets (in case of wotf) made of: header: 1 bit at ?0? b7-b0: 8-bit data pb: parity bit sent after data. xor between all b(i) ack: acknowledge figure 9. data format (target -> host) each data frame is made of: header: 1 bit at ?1? b7-b0: 8-bit data pb: parity bit sent after data ack: acknowledge b2 b1 b0 ack command 0 pb data1 b7 b6 b5 b4 b3 b2 b1 b0 pb ack ... ... 0 italic : bit sent by the host bold : bit sent by the device b7 b6 b5 b4 b3 b2 b1 b0 pb ack data n data n+1 1 ... ... data n-1 italic : bit sent by the host bold : bit sent by the device
UM0470 single wire interface module (swim) 11/37 3.5 swim commands the host can send a command when the line is idle or after each data byte from device. after sending the command, the host releases the line. when the swim is ready to answer to the command, it initiates the transfer. if a new command from the host occurs while a command is pending in swim, the pending co mmand is cancelled and the new command is decoded, except in case of wotf. three commands are available. they are listed in ta b l e 1 . 3.5.1 srst: system reset format: 1 command from host to target parameters: none. srst command generates a system reset only if swim_csr/swim_dm bit is set. 3.5.2 rotf: read on the fly format: 1 command followed by the number of bytes to be read followed by the address on three bytes. parameters: n the 8 bits are the number of bytes to read (from 1 to 255) @e/h/l: this is the 24-bit address to be accessed. d[...]: these are the data bytes read from the memory space if the host sends a nack to a data byte, the device will send the same byte again. if swim_dm bit is cleared, rotf can only be done on swim internal registers. 3.5.3 wotf: write on the fly 1 command followed by the number of bytes to be written followed by the address on three bytes. table 1. swim command summary command binary code srst 000 rotf 001 wotf 010 reserved for future use 011 1xx srst rotf n @e @h @l d[@] d[@+n] wotf n @e @h @l d[@] d[@+n]
single wire interface module (swim) UM0470 12/37 parameters: n the 8 bits are the number of bytes to write (from 1 to 255) @e/h/l: this is the 24-bit address to be accessed. d[...]: these are the data bytes to write in the memory space if a byte d [i] has not been written when th e following byte d [i+1] arrives, d [i+1] will be followed by a nack. in this case the host must send d [i+1] again until it is acknowledged. for the last byte, if it is not yet written when a new command occurs, the new command will receive a nack and will not be taken into account. if swim_dm bit is cleared, wotf can only be done on swim internal registers. 3.6 swim communication reset in case of a problem during communication, the host can reset the communication and the on-going command by sending 128 x hsi clock periods low on the swim pin. if the swim logic detects that the swim pin is low for mo re than 64 x hsi clock periods, it will reset the communication state machine and will s witch the swim to low-speed mode (swim_csr.hs <- 0). this is to allow for va riation in the frequency of the internal rc oscillator. in response to this communication reset, swim will send the synchronization frame which is 128x hsi oscillator periods low on dbg pin. 3.7 cpu register access the cpu registers are mapped in the stm8 memory, and they can be read or written directly using the rotf and wotf swim commands. write operations to the cpu registers are committed only when the cpu is stalled. to flush the instruction decode phase, you must set the flush bit in the dm control/status register 2 (dm_csr2) after writing a new value in the program counter (pce, pch, pcl). table 2. cpu register memory mapping in stm8 cpu register memory location a7f00h pce 7f01h pch 7f02h pcl 7f03h xh 7f04h xl 7f05h yh 7f06h yl 7f07h sph 7f08h spl 7f09h cc 7f0ah
UM0470 single wire interface module (swim) 13/37 3.8 swim communicat ion in halt mode to maintain the communicatio n link with the debug host, the hs i oscillator rema ins on when the mcu enters halt mode. this means that halt mode power consumption measurements have no meaning when the swim module is active. the no_access bit in the swim_csr register is set when the system is in halt, wfi or readout protection mode. this means the bus is not accessible in this case. the oscoff bit in the swim_csr re gister is used to switch off the oscillator. in this case, debug control is lost as long as the device is in halt mode and the swim pin is high. the only way to recover the debug control is to induce a falling ed ge on swim pin: this will re- enable the hsi oscillator.
single wire interface module (swim) UM0470 14/37 3.9 physical layer during the communication, the swim pin will be in pseudo-open drain configuration. the swim pin in the device is capable of sinking 8 ma when it drives the line to 0. the external pull-up on the swim line should be sized in such a way that the maximum rise time t r of the swim line should be less than 1 sampling period of the bit (which is 100 ns +/- 4 %). figure 10. timings on swim pin table 3. swim pin characteristics parameter symbol generic formula timings for hsi = 10 mhz lsi = 32 to 64 khz min max fall time on swim pin t f tbd 50 ns rise time on swim pin t r tbd 96 ns inter-bit time (the time which swim pin stays high between 2 bits) t ib tbd >0 inter-frame time (time between end of a frame and the next one) t if tbd 0 low time for a bit at 0 high speed: t b0 tbd 768 ns 832 ns low speed: t b0 tbd 1.6 s 2.4 s low time for a bit at 1 (high speed) high speed: tb1 tbd 192 ns 208 ns low speed: tb1 tbd 150 ns 250 ns injected current on swim pin tbd 8 ma t f t r t ib swim pin t b0 /t b1
UM0470 single wire interface module (swim) 15/37 3.10 stm8 swim registers 3.10.1 swim control stat us register (swim_csr) address: 7f80h reset value: 00h this register is reset only by a power on re set or by swim srst command if the rst bit =1 in the swim_csr register. 76543210 safe_mask no_access swim_dm hs oscoff rst hsit pri rw r rwrwrwrw r rw bit 7 safe_mask : mask internal reset sources this bit can be read or written through swim only. it cannot be accessed through the stm8 bus. it includes the watchdog reset. 0: internal reset sources are not masked 1: internal reset sources are masked bit 6 no_access : bus not accessible this bit can be read through swim only, to determine the bus is accessible or not. it is set automatically if the device is in halt, wfi or readout protection mode. 0: bus is accessible 1: bus is not accessible caution: depending on the swim module revision, in some devices, the no_access bit indicates only that the device is in halt mode. bit 5 swim_dm : swim for debug module this bit can be read or written to 1 through swim only. it cannot be accessed through the stm8 bus. 0: the swim module can access only swim_csr register. swim reset command has no effect 1: the whole memory range can be a ccessed with rotf and wotf commands. the srst command generates a reset bit 4 hs : high speed this bit can be read or written through swim only. it cannot be accessed through stm8 bus. 0: low speed bit format 1: high speed bit format the speed change occurs when the communicat ion is idle. it is reset by the swim communication reset condition as described in section 3.6 . bit 3 oscoff : oscillators off control bit this bit can be read or written through swim only. it cannot be accessed through stm8 bus. 0: hsi oscillator remains on in halt mode 1: hsi oscillator is not requested on in halt mode
single wire interface module (swim) UM0470 16/37 bit 2 rst : swim reset control bit this bit can be read or written through swim only. it cannot be accessed through stm8 bus. 0: swim is not reset when a srst command occurs. 1: swim is reset when a srst command occurs. swim will re-enter off mode. bit 1 hsit : high speed internal clock is trimmed this bit is read only through swim only. it cannot be accessed through stm8 bus. it is set when the hsit bit is set in the core configuration register and reset by an external reset. 0: high speed internal clock is not trimmed, swim must remain in low speed mode. 1: high speed internal clock is trimmed, swim high speed mode is allowed. bit 0 pri : swim access priority this bit can be read or written through swim only. usually the swim accesses to system resources are non-intrusive, swim having the lowest priority. this can be overridden by setting this bit. 0: non-intrusive access by swim to system resources (low priority) 1: intrusive access by swim to system resources (swim has priority, cpu is stalled). note: the iom bit is located in the stm8 core configuration register. refer to the corresponding datasheet for information on this register
UM0470 single wire interface module (swim) 17/37 3.10.2 swim clock control register (clk_swimccr) address offset: 50cdh (product dependent) reset value: xxxx 0000 (x0h) 76543210 reserved swimclk rw bits 7:1 reserved, must be kept cleared. bit 0 swimclk swim clock divider this bit is set and cleared by software. 0: swim clock divided by 2 1: swim clock not divided by 2 note: this register is not present in some stm8 devices.
debug module (dm) UM0470 18/37 4 debug module (dm) 4.1 introduction the debug module (dm) allows the developer to perform certain debugging tasks without using an emulator. for example, the dm can interrupt the mcu to break infinite loops or output the core context (stack) at a given point. the dm is mainly used for in-circuit debugging. 4.2 main features two conditional breakpoints (break on instruction fetch, data read or write, stack access...) software breakpoint control step mode external stall capability on wotf command in swim mode watchdog and peripherals control dm version identification capability interrupt vector table selection
UM0470 debug module (dm) 19/37 figure 11. debug module block diagram 4.3 debug the dm registers can be read and written only through the swim interface. stm8 core has no access to these registers. 4.3.1 reset once the swim is active and swim_dm bit is set in swim_csr register, a ?data read? breakpoint at the reset vector address is automatically set, due to the reset values of the debug module registers. this breakpoint can be used to initialize the debug session. 4.3.2 breakpoints the dm generates a stall to the core when a breakpoint is reached. when the processor is stalled, the host can read or modify any address in memory. access to the processor registers is explained in section 3.7: cpu register access . rst brw bk2f bk1f dm_csr1 dm_bk1 - biw bir bc0 bc1 - dm_cr1 breakpoint dm_bk2 dm stall/trap bc2 - watchdog control dm stf ste debug module (dm) cpu (from slave dm when available) dm stall watchdog dm_cr2 fv_rom fv_ram ext stall management ext stall enfctx peripherals (timers, usb,...) dm_enfct software swim emu/dma swim interface stm8 dm registers read/write reset logic logic logic . swbkf swbke break flag enable bit stall bit swtrap bit swtrf flag
debug module (dm) UM0470 20/37 to restart the program execution, the stall bit in dm_csr2 must be cleared using the wotf command of the swim protocol. 4.3.3 abort to use the abort function, the host must write the stall bit in the dm_csr2 using the swim wotf command. no interrupt is generated. the core is stalled in the current state. using the swim commands, the host can read and modify the status of the mcu. if the cpu registers must be modified, the procedure described in section 3.7: cpu register access has to be used. the host can restart the program execution by resetting the stall bit using the swim commands. 4.3.4 watchdog control using the wdgoff bit in the dm control register 1 (dm_cr1) you can configure the window watchdog and independent watchdog counters to be stopped while the cpu is stalled by the debug module. this bit must be set before the watchdogs are activated. if a watchdog is enabled by hardware watchdog option bit, the wdgoff bit has no effect on it. 4.3.5 interaction with swim the swim sends the status bit which indicates th e swim is active or not. when swim is not active, the dm will not generate any break/stall request to the cpu. 4.4 breakpoint decoding table table 4. decoding table for breakpoint interrupt generation dm_cr1 break conditions dm_csr1 bc2 bc1 bc0 bir biw bk1f bk2f brw 00000 disabled (reset state) 0 0 x 00001data write on @=bk1 and data=bk2l 1 0 0 00010data r ead on @=bk1 and data=bk2l 1 0 1 00011data r/w on @=bk1 and data=bk2l 1 00/1 00100instruction fetch bk1<=@<=bk2 1 0 x 00101data write on bk1<=@<=bk2 1 0 0 00110data r ead on bk1<=@<=bk2 1 0 1 00111data r/w on bk1<=@<=bk2 1 00/1 01000instruction fetch on @<= bk1 or bk2<=@ 1 0 x 01001data write on @<= bk1 or bk2<=@ 1 0 0 01010data r ead on @<= bk1 or bk2<=@ 1 0 1 01011data r/w on @<= bk1 or bk2<=@ 1 00/1 011xx disabled 0 0 x 10000instruction fetch on @=bk1 then on @=bk2 0 1 x 10001data write on @=bk1 or @=bk2 10 or 01 or 11 0
UM0470 debug module (dm) 21/37 10010data r ead on @=bk1 or @=bk2 10 or 01 or 11 1 10011data r/w on @=bk1 or @=bk2 10 or 01 or 11 0/1 10100instruction fetch on @=bk1 or @=bk2 10 or 01 or 11 x 10101instruction fetch on @=bk1 / data write on @=bk2 10 or 01 x-0 10110instruction fetch on @=bk1 / data r ead on @=bk2 10 or 01 x-1 10111instruction fetch on @=bk1 / data r/w on @=bk2 10 or 01 x-0/1 110xx disabled 0 0 x 11100data write in stack on @<=bk1 / instruction fetch on @=bk2 10 or 01 0-x 11101data write in stack on @<=bk1 / data write on @=bk2 10 or 01 or 11 0 11110data write in stack on @<=bk1 / data read on @=bk2 10 or 01 0-1 11111data write in stack on @<=bk1 / data r/w on @=bk2 10 or 01 or 11 0-0/1 table 4. decoding table for breakpoint interrupt generation dm_cr1 break conditions dm_csr1 bc2 bc1 bc0 bir biw bk1f bk2f brw
debug module (dm) UM0470 22/37 4.5 software breakpoint mode software breakpoint mode is reserved for debugging tools to insert breakpoints into user code by substituting a user instruction with a software break (reserved bkpt instruction #8b). software breakpoint mode is enabled using the swbkpe bit in the dm control/status register 2 (dm_csr2) . when a bkpt instruction is de coded, the cpu is stalled a nd the stall and swbkf bits are set by hardware to indicate that a software breakpoint has occurred. to resume execution, the debugger must restore the user's instruction, then set the flush bit and clear the stall bit.
UM0470 debug module (dm) 23/37 4.6 timing description this paragraph defines when the debug module stalls the cpu when using the different breakpoint sources. the stm8 instruction can be modelized in time with an op-code/operand fetch phase decode and execution phases as shown in figure 12 . the timing information is based on this models. figure 12. stm8 instruction model 4.7 abort the stall is generated immediately on writing the stall bit in the dm_csr2 register. figure 13. stm8 debug module stall timing 4.8 data breakpoint a stall is generated when swim is active, after the end of the current instruction execution. figure 14. stm8 dm data break timing op-code/operand decode execute fetch t (1 to 10 t cpu ) instruction 1-5 bytes (1-2 t cpu ) (1to5t cpu ) t instruction 1 instruction 2 instruction 3 stall request dm stall generated t data break request stall generated dec2.n d_rd1 exe2.1 d_wr1 fetch2 ...exe3(stalled)...
debug module (dm) UM0470 24/37 4.9 instruction breakpoint in the stm8, on an instruction break, dm stalls the cpu before the selected instruction execution (while the instruction is in the decode stage). see figure 15 . note: when the specified address does not correspond to a valid instruction address, no stall is generated. figure 15. stm8 dm instruction break timing t instruction break request /stall request = dm servicing dec2 dec1 exe1 ... exec2 (stalled)
UM0470 debug module (dm) 25/37 4.10 step mode the stm8 cpu stall is activated before the inst ruction execution, in the first decode cycle of the instruction. see figure 16 . figure 16. stm8 dm step timing note: when step mode and instruction break on the next instruction mode are both enabled, both the stf and the bkxf flags are set. when you clear the stall bit, the step function continues its normal operation. t step 1st dm dec1 exec1 dec2 dec2 dec2 exec2 exec2 exec2 dec4 2nd dm break 3rd dm break exec4 served/ served/ 1st dm break served enable 4th dm break served/ cpu stalled cpu stalled cpu stalled cpu stalled dec2 dec3 exec2 exec3
debug module (dm) UM0470 26/37 4.11 application notes 4.11.1 illegal memory access to verify if the program attemp ts to write or read in an ille gal part of memory (reserved area), select the ?data r/w on bk1<=@<=bk2? condition, where bk1 and bk2 are the lower and upper addresses of the reserved memory. 4.11.2 forbidden stack access if part of the stack contains specific data or instructions that should not be overwritten, the dm can be used to prevent access to these locations. select one of the ?data write in stack on @<=bk1? conditions and set bk1 to the upper value where the specific data are located in the stack. if the stm8 tries to overwrite these values (after an interrupt or a call...), dm will generate a break. the four possible associ ated conditions allow to manage another breakpoint capability at the same time. 4.11.3 dm break after an dm break, the cpu is stalled (thr ough the emu_stall signal). while the cpu is stalled, the swim can read/write any memory location or memory mapped register. the program can be continued from the breakpoint, by resetting the stall bit. if a change of pc is needed, the swim must write the new pc value using the method described in section 3.7: cpu register access . in order to fetch the code from the new pc address, the swim must set the flush bit in the dm control/status register 2 (dm_csr2) before resetting the stall bit .
UM0470 debug module (dm) 27/37 4.12 dm registers these registers are read/write only through the swim interface. in this section, the following abbreviations are used: read/write (rw) swim can read and write to these bits via the rotf/wotf commands. read-only (r) swim can only read these bits via the rotf command.
debug module (dm) UM0470 28/37 4.12.1 dm breakpoint register 1 extended byte (dm_bkr1e) stm8 address: 7f90h reset value: 1111 1111 (ffh) 4.12.2 dm breakpoint regist er 1 high byte (dm_bkr1h) address: 7f91h reset value: 1111 1111 (ffh) 4.12.3 dm breakpoint regist er 1 low byte (dm_bkr1l) address: 7f92h reset value: 1111 1111 (ffh) 76543210 bk1[23:16] rw rw rw rw rw rw rw rw bits 7:0 bk1[23:16] : breakpoint 1 extended byte value this register is written by software to define the extended 8 address bits of breakpoint 1. 76543210 bk1[15:8] rw rw rw rw rw rw rw rw bits 7:0 bk1[15:8] : breakpoint 1 high byte value this register is written by software to define the higher 8 address bits of breakpoint 1. 76543210 bk1[7:0] rw rw rw rw rw rw rw rw bits 7:0 bk1[7:0] : breakpoint 1 high byte value this register is written by software to define the lower 8 address bits of breakpoint 1.
UM0470 debug module (dm) 29/37 4.12.4 dm breakpoint register 2 extended byte (dm_bkr2e) address: 7f93h reset value: 1111 1111 (ffh) 4.12.5 dm breakpoint regist er 2 high byte (dm_bkr2h) address: 7f94h reset value: 1111 1111 (ffh) 4.12.6 dm breakpoint regist er 2 low byte (dm_bkr2l) address: 7f95h reset value: 1111 1111 (ffh) 76543210 bk2[23:16] rw rw rw rw rw rw rw rw bits 7:0 bk2[23:16] : breakpoint 2 extended byte value this register is written by software to define the extended 8 address bits of breakpoint 2. 76543210 bk2[15:8] rw rw rw rw rw rw rw rw bits 7:0 bk2[15:8] : breakpoint 2 high byte value this register is written by software to define the higher 8 address bits of breakpoint 2. 76543210 bk2[7:0] rw rw rw rw rw rw rw rw bits 7:0 bk2[7:0] : breakpoint 2 high byte value this register is written by software to define the lower 8 address bits of breakpoint 2.
debug module (dm) UM0470 30/37 4.12.7 dm control r egister 1 (dm_cr1) address: 7f96h reset value: 0000 0000 (00h) 76543210 wdgoff reserved bc[2:0] bir biw reserved rw - rwrwrwrwrw bit 7 wdgoff watchdog control enable. this bit must be set or cleared by software before the watchdogs (wwdg and/or iwdg) are activated. this bit has no ef fect if the hardware watchdog option is selected. 0: watchdog counters are not stopped while cpu is stalled by dm 1: watchdog counters are stopped while cpu is stalled by dm bit 6 reserved. bits 5:3 bc[2:0] breakpoint control these bits are set and cleared by software, they are used to configure the breakpoints as shown in ta b l e 4 . bit 2 bir break on read control this bit enables a breakpoint on a data read operation. it is set and cleared by software. 0: no break on data read 1: break on data read bit 1 biw break on write control this bit enables a breakpoint on a data write operation. it is set and cleared by software. 0: no break on data write 1: break on data write bit 0 reserved .
UM0470 debug module (dm) 31/37 4.12.8 dm control r egister 2 (dm_cr2) address: 7f97h reset value: 0000 0000 (00h) 76543210 reserved fv_rom reserved fv_ram rw rw bit 7:3 these bits are reserved and must be kept at 0. bit 2 fv_rom remap vector table in rom . this bit is set or cleared by software. it remaps the vector table to a rom location (product dependent) instead of program memory (usually 8000h). 0: vector table is in program memory area (8000h) 1: vector table is in rom memo ry area (depends on the product) bit 1 reserved, must be kept at 0. bit 0 fv_ram remap vector table in ram this bit is set or cleared by software. it remaps the interrupt vector table to a ram location instead of program memory (usually 8000h). 0: vector table is in program memory area (8000h) 1: vector table is in ram memory area (address depends on the product)
debug module (dm) UM0470 32/37 4.12.9 dm control/stat us register 1 (dm_csr1) address: 7f98h reset value: 0001 0000 (10h) 76543210 reserved ste stf rst brw bk2f bk1f reserved rwrwrrrr bit 7 reserved. bit 6 ste step mode enable (read / write) this bit is set and cleared by software. it enables step mode. 0: step mode disabled 1: step mode enabled bit 5 stf step flag (read only) this bit indicates that the stall was generated by step mode. it is set and cleared by hardware. writing to this bit does not change the bit value. 0: step mode stall did not occur 1: step mode stall occurred bit 4 rst reset flag (read only) this bit is set by hardware when the cpu was stalled by the debug module (dm), just after reset. it is cleared by hardware when the stall bit is cleared. writing to this bit does not change the bit value. 0: no reset occurred 1: a reset occurred bit 3 brw break on read/write flag (read only) . this bit gives the value of the read/write signal when a break occurs. its value is not significant for instruction fetch breaks. it is set by hardware depending on the breakpoint conditions (see table 4: decoding table for breakpoint interrupt generation on page 20 ) and is cleared by hardware depending on the next breakpoint conditions. writing to this bit does not change the bit value. 0: breakpoint on write 1: breakpoint on read bit 2 bk2f breakpoint 2 flag (read only) . this bit indicates that the dm stall was generated by breakpoint 2. it is set by hardware depending on the control conditions (see table 4: decoding table for breakpoint interrupt generation on page 20 ) and is cleared by hardware when the stall bit is cleared. writing to this bit does not change the bit value. 0: breakpoint 2 did not occur 1: breakpoint 2 occurred bit 1 bk1f breakpoint 1 flag (read only) . this bit indicates that the dm interrupt was generated by breakpoint 1. it is set by hardware depending on the control conditions (see table 4: decoding table for breakpoint interrupt generation on page 20 ) and is cleared by hardware when the stall bit is cleared. writing to this bit does not change the bit value. 0: breakpoint 1 did not occur 1: breakpoint 1 occurred bit 0 reserved
UM0470 debug module (dm) 33/37 4.12.10 dm control/stat us register 2 (dm_csr2) address: 7f99h reset value: 0000 0000 (00h) 76543210 reserved swbrk swbkf stall reserved flush rw r r rw bits 7:6 reserved. must be kept at 0 bit 5 swbke software breakpoint control bit (read/write) this bit is used to enable/disable the software breakpoint capability with nop instruction 0: dm does not generate any event when no p(sw brk) instruction is fetched by cpu 1: dm generates an event (cpu stalled in swim mode) when a software break instruction is fetched by cpu. bit 4 swbkf software breakpoint status bit (read only) this flag is set when the cpu executes the software break instruction. 0: no software break instruction detected. 1: software break instructio n detected. this bit is cleared when the stall bit is cleared. bit 3 stall cpu stall control bit (r/w only in swim mode) this bit is used to stall the cpu. this bit is kept cleared if the device is not in swim mode. this bit is set by wotf command to generate an abort equivalent command it is also set by an dm trap interrupt event. this bit is cleared by wotf co mmand to re-start the cpu. 0: cpu runs normally 1: cpu is stalled bit: 2:1 reserved. must be kept at 0 bit: 10 flush flush decode this bit is set by software to flush the instruction decode phase after a pc modification. it is cleared by hardware when the flush is completed. 0: default status 1: flush decode
debug module (dm) UM0470 34/37 4.12.11 dm enable functi on register (dm_enfctr) address: 7f9ah reset value: 1111 1111 (ffh) 7 0 enfct7 enfct6 enfct5 enfct4 enfct3 enfct2 enfct1 enfct0 rw rw rw rw rw rw rw rw bits 7:0 enfctx enable function this bit is set and cleared by software. it allows to freeze a particular function of a peripheral when the core is stalled. the enfctx bit definitions are product dependent. 0: function is frozen when cpu is stalled by dm 1: function is active
UM0470 debug module (dm) 35/37 4.12.12 summary of swim, dm and core r egister maps table 5. stm8 registers stm8 address register name 76543210 7f00h a reset value a7 0 a6 0 a5 0 a4 0 a3 0 a2 0 a1 0 a0 0 7f01h pce (1) pc23 pc22 pc21 pc20 pc19 pc18 pc17 pc16 7f02h pch (1) pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 7f03h pcl (1) pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 7f04h xh reset value x15 0 x14 0 x13 0 x12 0 x11 0 x10 0 x9 0 x8 0 7f05h xl reset value x7 0 x6 0 x5 0 x4 0 x3 0 x2 0 x1 0 x0 0 7f06h yh reset value y15 0 y14 0 y13 0 y12 0 y11 0 y10 0 y9 0 y8 0 7f07h yl reset value y7 0 y6 0 y5 0 y4 0 y3 0 y2 0 y1 0 y0 0 7f08h sph (1) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 7f09h spl (1) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 7f0ah cc reset value v 0 - 0 i1 1 h 0 i0 1 n 0 z 0 c 0 7f80h swim_csr reset value safe_mask 0 no_access 0 swim_dm 0 hs 0 oscoff 0 rst 0 hsit 0 pri 0 7f90h dm_bk1re reset value bk1r23 1 bk1r22 1 bk1r21 1 bk1r20 1 bk1r19 1 bk1r18 1 bk1r17 1 bk1r16 1 7f91h dm_bk1rh reset value bk1r15 1 bk1r14 1 bk1r13 1 bk1r12 1 bk1r11 1 bk1r10 1 bk1r9 1 bk1r8 1 7f92h dm_bk1rl reset value bk1r7 1 bk1r6 1 bk1r5 1 bk1r4 1 bk1r3 1 bk1r2 1 bk1r1 1 bk1r0 1 7f93h dm_bk2re reset value bk2r23 1 bk2r22 1 bk2r21 1 bk2r20 1 bk2r19 1 bk2r18 1 bk2r17 1 bk2r16 1 7f94h dm_bk2rh reset value bk2r15 1 bk2r14 1 bk2r13 1 bk2r12 1 bk2r11 1 bk2r10 1 bk2r9 1 bk2r8 1 7f95h dm_bk2rl reset value bk2r7 1 bk2r6 1 bk2r5 1 bk2r4 1 bk2r3 1 bk2r2 1 bk2r1 1 bk2r0 1 7f96h dm_cr1 reset value wdgoff 0 reserved 0 bc2 0 bc1 0 bc0 0 bir 0 biw 0 reserved 0 7f97h dm_cr2 reset value reserved fv_rom 0 reserved 0 fv_ram 0 7f98h dm_csr1 reset value reserved 0 ste 0 stf 0 rst 0 brw 0 bk2f 0 bk1f 0 reserved 0 7f99h dm_csr2 reset value reserved 0 reserved 0 swbke 0 swbkf 0 stall 0 res reserved 0 flush 0 7f9ah dm_enfctr reset value enfct7 1 enfct6 1 enfct5 1 enfct4 1 enfct3 1 enfct2 1 enfct1 1 enfct0 1 1. the reset value for the sp and pc registers is product dependent. refer to the device datasheet for more details
revision history UM0470 36/37 5 revision history table 6. document revision history date revision changes 15-jan-2008 1 initial release.
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